The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of forming a fin-type field-effect transistor.
Device structures for a field-effect transistor generally include a body region, a source and a drain defined in the body region, and a gate electrode configured to switch carrier flow in a channel formed during operation in the body region. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in the channel between the source and drain to produce a device output current. For a planar field-effect transistor, the body region and channel are located beneath the top surface of a substrate on which the gate electrode is supported.
A fin-type field-effect transistor (FinFET) is a non-planar device structure that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET may include one or more fins composed of semiconductor material, heavily-doped source/drain regions, and a gate electrode that wraps about a channel located in the fin body between the source/drain regions. The arrangement between the gate electrode and fin body improves control over the channel and reduces the leakage current when the FinFET is in its ‘Off’ state in comparison with planar transistors. This, in turn, enables the use of lower threshold voltages than in planar transistors, and results in improved performance and lowered power consumption.
The fins of a FinFET are partially buried in an isolation layer of dielectric material that is applied after the fins are formed and before the source/drain regions are formed by epitaxial growth. The clean and etch processes associated with the formation of the source/drain regions may recess the isolation layer and introduce gouges and voids in the isolation layer, which introduces holes in the body region. The gouges and voids in the isolation layer and the holes in the body region may subsequently become filled by a conductor, which can cause electrical shorts between adjacent gate electrodes or between a gate electrode and an adjacent interconnect contact extending to a source/drain region.